The present invention relates to a method for forming a transistor of a semiconductor device, and more specifically, to a method for forming a transistor having a recess gate using a double patterning technology to overcome the resolution limit of a photolithography process.
As the design rule becomes smaller, the current technology for manufacturing a semiconductor device represents a limit in resolution in a photolithography process by the design rule of 80 nm in a DRAM manufacturing process. In a pattern of 60 nm or less, an immersion process should be applied to several processes for forming various layers of a semiconductor device, which results in a requirement of expensive equipment.
A double patterning technology which is one of dry processes can be applied with the existing equipment to form a fine pattern.
As the integration of semiconductor devices increases, the channel length of transistors becomes shorter. As a result, a threshold voltage of the transistor becomes lower, which is called a short channel effect. In order to prevent the short channel effect, a recess is formed in a cell region of a semiconductor substrate, thereby obtaining a transistor having a recess gate so that the channel length may be longer.